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SV51008
2014.01.10
DQS Phase-Shift
7-17
DLL
Center
PLL
Corner
Left
CLKIN
Center
Right
DLL_BR
CEN_X96_Y11
CEN_X96_Y2
COR_X208_Y10
COR_X208_Y1
—
CLK4P
CLK5P
CLK8P
CLK9P
CLK6P
CLK7P
CLK10P
CLK11P
DLL_BL
CEN_X96_Y11
CEN_X96_Y2
COR_X0_Y10
COR_X0_Y1
CLK0P
CLK1P
CLK4P
CLK5P
—
CLK2P
CLK3P
CLK6P
CLK7P
DQS Phase-Shift
The DLL can shift the incoming DQS signals by 0°, 45°, 90°, or 135°. The shifted DQS signal is then used as
the clock for the DQ IOE input registers.
All DQS/CQ/CQn pins referenced to the same DLL, can have their input signal phase shifted by a different
degree amount but all must be referenced at one particular frequency. For example, you can have a 90° phase
shift on DQS1T and a 45° phase shift on DQS2T, referenced from a 300-MHz clock. However, not all phase-
shift combinations are supported. The phase shifts on the DQS pins referenced by the same DLL must all
be a multiple of 45° (up to 135°).
The 7-bit DQS delay settings from the DLL vary with PVT to implement the phase-shift delay. For example,
with a 0° shift, the DQS/CQ signal bypasses both the DLL and DQS logic blocks. The Quartus II software
automatically sets the DQ input delay chains, so that the skew between the DQ and DQS/CQ pins at the DQ
IOE registers is negligible if a 0° shift is implemented. You can feed the DQS delay settings to the DQS logic
block and logic array.
The shifted DQS/CQ signal goes to the DQS bus to clock the IOE input registers of the DQ pins. The signal
can also go into the logic array for resynchronization if you are not using IOE resynchronization registers.
External Memory Interfaces in Stratix V Devices
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